This application relies for priority upon Korean Patent Application No. 1999-48932, filed on Nov. 5, 1999, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a mask ROM device and, more particularly, to a mask ROM device which is synchronous operable with a clock signal.
A mask ROM device as a non-volatile memory device has been used for a program storage element or BIOS chip, having variable bit structure. Techniques with variable bit structure of the mask ROM device are disclosed in xe2x80x9cKM23V16205CSGxe2x80x9d and xe2x80x9cKM23V32005BGxe2x80x9d in SAMSUNG DATA BOOK, published on February 1995. As disclosed in the reference, the mask ROM device is an asynchronous memory device in a typical trend. According to the number of bits of output data, the mask ROM device has a single word mode (xc3x9716) or a double word mode (xc3x9732). Alternative one of the single and double word modes is selected dependent on a voltage level at an external pin {overscore (WORD)} that is provided to the device.
The asynchronous mask ROM device generally includes a memory cell array for storing data. When the device is operating in the double word mode, double word data (i.e., 32 data bits) read out from the memory cell array is simultaneously supplied to the outside of the device by one read command. On the other hand, when a general mask ROM device is operating in the single word mode, the read-out double word data is turned out of the device in twice by two read commands. That is, higher one (or lower significant one) of the read-out word data is output thereof. To avoid collision with data associated with a previous read command, lower (or upper) one of the read-out word data is output turned out of the device after a predetermined time.
It is recently required for semiconductor memory devices to be operable in a higher bandwidth. A system clock signal used in a system to which a mask ROM device is applied also supplied to the mask ROM device in order to respond to the demand for a fast operation. If a mask ROM device synchronized with a clock signal is operating in the single word mode, the higher significant (or the lower) word data and lower (upper) word data are consecutively (without discontinuity or data-to-data collision) turned out of the device to achieve much faster operation speed.
Therefore, it is an object of the present invention to provide a synchronous mask ROM which can carry out consecutive read operations in a single word mode.
According to one aspect of the invention, a synchronous mask ROM has a double word mode wherein double word data is output during one cycle of an external clock signal, and a single word mode wherein single word data is output during one cycle the external clock signal. The device carries out a read operation during the single word mode. The device includes a word decoder and a selection circuit. During the read operation of the single word mode, the word decoder holds a word signal at a disable interval of an internal clock signal of which a clock cycle is earlier by 2 clock cycles than a clock cycle corresponding to a predetermined CAS latency by 2 clock cycles after an occurrence of a read command. And, the word decoder generates selection signals of complementary logic states in response to the held word signal and a mode selection signal. The mode selection signal selects one of the single word mode and the double word mode, and the word signal selects one of the lower word data and the higher word data. During the read operation of the single word mode, the selection signal transfers the higher/lower one of the data (sensed by a sense amplifier circuit) corresponding to columns selected by a column selection circuit to an output buffer circuit in response to the selection signals, and consecutively transfers the upper/lower data to the output buffer circuit.
The word decoder generates a latency flag signal in response to the column address strobe signal. The word decoder includes: a latency signal generation unit which enables the latency flag signal when the column address strobe signal is enabled, and disables the latency flag signal according to low-to-high transition of an internal clock signal earlier 2 clock cycles than a clock cycle corresponding to a predetermined CAS latency, the internal clock signal enabling the latency flag signal when the column address strobe signal is enabled; a latch signal generation unit which generates a word latch signal with a pulse form when the latency flag signal is disabled; and a selection signal generation unit which holds the word signal when the word latch signal is enabled, and enables one of the selection signals in response to the held word signal and the mode selection signal during the read operation of the single word mode.
The word latch signal is enabled at high-to-low transition of an internal clock signal earlier by 2 clock cycles corresponding to a predetermined CAS latency, and is disabled at low-to-high transition of the internal clock signal earlier by 1 clock cycle than a clock cycle corresponding to a predetermined CAS latency.
The output buffer circuit receives data transferred via the selection circuit at only low-to-high transition of the internal clock signal.
According to the device, it is possible to the output lower (or higher) word data, and then consecutively output the higher (or lower) word data without collision of the lower (or higher) word data with the lower (or higher) word data during the read operation of the single word mode.